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| 3UHOLPLQDU\#LQIRUPDWLRQ (R) $65<)373 89#845.;#&026#)ODVK#((3520 )HDWXUHV * Organization:512K words x 8 bits * Industrial and commercial temperature * Sector architecture - Eight 64K byte sectors - Erase any combination of sectors or full chip * Single 5.00.5V power supply for read/write operations * Sector protection * High speed 55/70/90/120/150 ns address access time * Automated on-chip programming algorithm - Automatically programs/verifies data at specified address * Automated on-chip erase algorithm - Automatically preprograms/erases chip or specified sectors * 10,000 write/erase cycle endurance * Low power consumption - 30 mA maximum read current - 60 mA maximum program current - 400 A typical standby current * JEDEC standard software, packages and pinouts - 32-pin TSOP - 32-pin PLCC * Detection of program/erase cycle completion - DQ7 DATA polling - DQ6 toggle bit * Erase suspend/resume - Supports reading data from or programming data to a sector not being erased * Low VCC write lock-out below 2.8V )/$6+ )/$6+ )/$6+ )/$6+ /RJLF#EORFN#GLDJUDP VCC VSS Sector protect switches Erase voltage generator Program/erase control Command register CE OE Program voltage generator Chip enable Output enable Logic STB Data latch DQ0-DQ7 3LQ#DUUDQJHPHQW A11 A9 A8 A13 A14 A17 WE VCC A18 A16 A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 A7 A6 A5 A4 A3 A2 A1 Input/output buffers AS29F040 WE 32-pin PLCC A12 A15 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 DQ1 DQ2 VSS DQ3 DQ4 DQ5 DQ6 3 2 A16 A18 1 VCC WE 32 31 30 29 28 27 26 25 24 23 22 21 A14 A13 A8 A9 A11 OE A10 CE DQ7 A17 32-pin TSOP Y gating VCC detector Timer Address latch STB Y decoder AS29F040 X decoder Cell matr A0 DQ0 A0-A18 6HOHFWLRQ#JXLGH AS29F040-55 Maximum access time Maximum chip enable access time Maximum output enable access time tAA 55 tCE 55 tOE 25 AS29F040-70 70 70 30 AS29F040-90 90 90 35 AS29F040-120 AS29F040-150 Unit 120 120 50 150 150 55 ns ns ns ','#440533440$1#728233 $//,$1&(#6(0,&21'8&725 4 Copyright (c)2000 Alliance Semiconductor. All rights reserved. $65<)373 (R) 3UHOLPLQDU\#LQIRUPDWLRQ )XQFWLRQDO#GHVFULSWLRQ The AS29F040 is a 4-megabit, 5-volt-only Flash memory device organized as 512K bytes of 8 bits each. For flexible erase an program capability, the 4 megabits of data is divided into eight 64K-byte sectors. The x8 data appears on DQ0-DQ7. The AS29F040 is offered in JEDEC standard 32-pin TSOP and 32-pin PLCC packages. This device is designed to be programmed an erased in-system with a single 5.0V VCC supply. The device can also be reprogrammed in standard EPROM programmers. The AS29F040 offers access times of 55/70/90/120/150 ns, allowing 0-wait state operation of high-speed microprocessors. To eliminate bus contention the device has separate chip enable (CE), write enable (WE), and output enable (OE) controls The AS29F040 is fully compatible with the JEDEC single power supply Flash standard. Write commands to the command register use standard microprocessor write timings. An internal state machine uses register contents to control the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Read data operates from the device in the same manner as other Flash or EPROM devices. The program command sequence is used to invoke the automated on-chip programming algorithm that automatically times the program pulse widths and verifies proper cell margin. The erase command sequence is used to invoke the automated on-chip erase algorithm that preprograms the sector if it is not already programmed before executing the erase operation, times the erase pulse widths, and verifies proper cell margin. Sector erase architecture allows specified sectors of memory to be erased and reprogrammed without altering data in other sector s. A sector typically erases and verifies within 1.0 seconds. Hardware sector protection disables both program and erase operations in any or all combinations of the eight sectors. The device provides true background erase with Erase Suspend, which puts erase operations on hold to either read data from or program data to a sector that is not being erased. The chip erase command will automatically erase all unprotected sectors. A factory shipped AS29F040 is fully erased (all bits = 1). The programming operation sets bits to 0. Data is programmed into the array one byte at a time in any sequence and across sector boundaries. A sector must be erased to change bits from 0 to 1. Erase returns all bytes in a sector to the erased state (all bits = 1). Each sector is erased individually with no effect on other sectors. The device features single 5.0V power supply operation for read, write, and erase functions. Internally generated and regulate voltages are provided for the program and erase operations. A low VCC detector automatically inhibits write operations during power transtitions. DATA polling of DQ7 or toggle bit (DQ6) may be used to detect end-of-program or erase operations. The device automatically resets to read mode after program and/or erase operations are completed. The AS29F040 resists accidental erasure or spurious programming signals resulting from power transitions. Control register architecture permits the alteration of memory contents only after successful completion of specific command sequences. During power up, the device is set to read mode with all program and/or erase commands disabled when VCC is less than V LKO (lockout voltage). The command registers are not affected by noise pulses of less than 5 ns on OE, CE, or WE. CE and WE must be logical zero and OE a logical one to initiate write commands. The AS29F040 uses Fowler-Nordheim tunnelling to electrically erase all bits within a sector simultaneously. Bytes are programme one at a time using the EPROM programming mechanism of hot electron injection. )/$6+ 5 $//,$1&(#6(0,&21'8&725 ','#440533440$1#728233 0DUFK#5333 (R) $65<)373 2SHUDWLQJ#PRGHV Mode ID read MFR code ID read device code Read Standby Output disable Write Enable sector protect Sector unprotect Verify sector protect CE L L L H L L L L L OE L L L X H H VID VID L WE H H H X H L Pulse/L Pulse/L H A0 L H A0 X X A0 L L L A1 L L A1 X X A1 H H H A6 L L A6 X X A6 L H L A9 VID VID A9 X X A9 VID VID VID DQ0-DQ7 Code Code DOUT High Z High Z DIN X X Code )/$6+ )/$6+ )/$6+ )/$6+ )/$6+ )/$6+ )/$6+ )/$6+ L = Low ( 0RGH#GHILQLWLRQV Item ID MFR code, device code Read mode Description Selected by A9 = VID(11.5-12.5V), CE = OE = A1 = A6 = L, enabling outputs. When A0 is low (VIL) the output data = 52h, a unique Mfr. code for Alliance Semiconductor Flash products. When A0 is high (VIH), DOUT represents the device code for the AS29F040. Selected with CE = OE = L, WE = H. Data is valid in tACC time after addresses are stable, tCE after CE is low and tOE after OE is low. Selected with CE = H. Part is powered down, and ICC reduced to <1.0 mA for TTL input levels and <100 A for CMOS levels. If activated during an automated on-chip algorithm, the device completes the operation before entering standby. Selected with CE = WE = L, OE = H. Accomplish all Flash erasure and programming through the command register. Contents of command register serve as inputs to the internal state machine. Address latching occurs on the falling edge of WE or CE, whichever occurs late . Data latching occurs on the rising edge WE or CE, whichever occurs first. Filters on WE prevent spurious noise events from appearing as write commands. Hardware protection circuitry implemented with external programming equipment causes the device to disable program and erase operations for specified sectors. Disables sector protection for all sectors using external programming equipment. All sectors must be protected prior to sector unprotection. Verifies write protection for sector. Sectors are protected from program/erase operations on commercial programming equipment. Determine if sector protection exists in a system by writing the ID read command sequence and reading location XXX02h, where address bits A16-18 select the defined sector addresses. A logical 1 on DQ0 indicates a protected sector; a logical 0 indicates an unprotected sector. Standby Output disable Part remains powered up; but outputs disabled with OE pulled high. Write Enable sector protect Sector unprotect Verify sector protect ','#440533440$1#728233 $//,$1&(#6(0,&21'8&725 6 $65<)373 (R) 3UHOLPLQDU\#LQIRUPDWLRQ 6HFWRU#DUFKLWHFWXUH#DQG#DGGUHVV#WDEOH Equal sector architecture Sector Addresses 00000h-0FFFFh 10000h-1FFFFh 20000h-2FFFFh 30000h-3FFFFh 40000h-4FFFFh 50000h-5FFFFh 60000h-6FFFFh 70000h-7FFFFh Size (Kbytes) 64 64 64 64 64 64 64 64 A18 0 0 0 0 1 1 1 1 0 1 2 3 4 5 6 7 ID sector address A17 0 0 1 1 0 0 1 1 A16 0 1 0 1 0 1 0 1 )/$6+ 5($'#FRGHV Mode MFG code (Alliance Semiconductor) Device code Sector protection A18-A16 X X Sector address A9 VID VID VID A8-A7 X X Sector address A6 L L L A5-A2 X X Sector address A1 L L H A0 L H L Code on DQ0-DQ7 52h A4h 01h protected 00h unprotected L = Low ( &RPPDQG#IRUPDW Command sequence Reset/read Reset/read Required bus cycles 1 4 1st bus write cycle Address XXXXh 5555h Data F0h AAh 2nd bus write cycle Address Read Address 2AAAh Data Read Data 55h 5555h F0h Read Address 00h MFR code Autoselect ID read 4 5555h AAh 2AAAh 55h 5555h 90h 01h Device code XXX02h Sector protection 4 6 6 1 1 5555h 5555h 5555h XXXXh XXXXh AAh AAh AAh B0h 30h 2AAAh 2AAAh 2AAAh 55h 55h 55h 5555h 5555h 5555h A0h 80h 80h Program Address 5555h 5555h Read Data 52h A4h 01 = protected 00 = unprotected Program Data AAh AAh 2AAAh 2AAAh 55h 55h 5555h Sector Address 10h 30h 3rd bus write cycle Address Data 4th bus read/write cycle Address Data 5th bus write cycle Address Data 6th bus write cycle Address Data Program Chip erase Sector erase Sector erase suspend Sector erase resume 1 2 3 4 5 6 Bus operations defined in "Mode definitions," on page 3. Reading from or programming to non-erasing sectors allowed in Erase Suspend mode. Address bit A15 = X = Don't care for all address commands except Program Address. Address bit A16 = X = Don't care for all address commands except Program Address and Sector Address. Address bit A17 = X = Don't care for all address commands except Program Address and Sector Address. Address bit A18 = X = Don't care for all address commands except Program Address and Sector Address. 7 $//,$1&(#6(0,&21'8&725 ','#440533440$1#728233 0DUFK#5333 (R) $65<)373 &RPPDQG#GHILQLWLRQV Item Description Initiate read or reset operations by writing the read/reset command sequence into the command register. This allows the microprocessor to retrieve data from the memory. Device remains in read mode until command register contents are altered. Device automatically powers up in read/reset state. This feature allows only reads, therefore ensuring no spurious memory content alterations during power up. AS29F040 provides manufacturer and device codes in two ways. External PROM programmers typically access the device codes by driving +12V on A9. AS29F040 also contains an ID read command to read the device code with only +5V, since multiplexing +12V on address lines is generally undesirable. ID read Initiate device ID read by writing the ID read command sequence into the command register. Follow with a read sequence from address XXX00h to return MFG code. Follow ID read command sequence with a read sequence from address XXX01h to return device code. To verify write protect status on sectors, read address XXX02h. Sector addresses A18-A16 produc e a1 on DQ0 for protected sector and a 0 for unprotected sector. Exit from ID read mode with Read/Reset command sequence. Programming the AS29F040 is a four bus cycle operation performed on a byte-by-byte basis. Two unlock write cycles precede the program setup command and program data write cycle. Upon execution of the program command, no additional CPU controls or timings are necessary. Addresses are latched on the falling edge of CE or WE, whichever is last; data is latched on the rising edge of CE or WE, whichever is first. The AS29F040's automated on-chip program algorithm provides adequate internally-generated programming pulses and verifies the programmed cell margin. Byte/word programming Check programming status by sampling data on the DATA polling (DQ7), or toggle bit (DQ6). The AS29F040 returns the equivalent data that was written to it (as opposed to complemented data), to complete the programming operation. The AS29F040 ignores commands written during the programming operation. AS29F040 allows programming in any sequence, across any sector boundary. Changing data from 0 to 1 requires an erase operation. Attempting to program data 0 to 1 results in DQ5 = 1 (exceeded programming time limits); reading this data after a read/reset operation returns a 0. When programming time limit is exceeded, DQ5 reads high, and DQ6 continues to toggle. In this state , areset command returns the device to read mode. Chip erase requires six bus cycles: two unlock write cycles; a setup command, two additional unlock write cycles; and finally the Chip erase command. Chip erase Chip erase does not require logical 0s to be written prior to erasure. When the automated on-chip erase algorithm is invoked with the Chip erase command sequence, AS29F040 automatically programs and verifies the entire memory array for an all-zero pattern prior to erase. The AS29F040 returns to read mode upon completion of chip erase unless DQ5 is set high as a result of exceeding time limit. )/$6+ )/$6+ )/$6+ )/$6+ )/$6+ )/$6+ )/$6+ )/$6+ Reset/read ','#440533440$1#728233 $//,$1&(#6(0,&21'8&725 8 $65<)373 (R) 3UHOLPLQDU\#LQIRUPDWLRQ Item Description Sector erase requires six bus cycles: two unlock write cycles, a setup command, two additional unlock write cycles, and finally the sector erase command. Identify the sector to be erased by addressing any location in the sector. The address is latched on the falling edge of WE; the command, 30h, is latched on the rising edge of WE. The sector erase operation begins after a 80 s time-out. To erase multiple sectors, write the sector erase command to each of the addresses of sectors to erase after following the six bus cycle operation above. Timing between writes of additional sectors must be <80 s, or the AS29F040 ignores the command and erasure begins. During the erase time-out period any falling edge of WE resets the time-out. Any command (other than sector erase or erase suspend) during the time-out period resets the AS29F040 to read mode, and the device ignores the sector erase command string. Erase such ignored sectors by restarting the sector erase command on the ignored sectors. The entire array need not be written with 0s prior to erasure. AS29F040 writes 0s to the entire sector prior to electrical erase; writing of 0s affects only selected sectors, leaving non-selected sectors unaffected. AS29F040 requires no CPU control or timing signals during sector erase operations. Automatic sector erase begins after erase time-out from the last rising edge of WE from the sector erase command stream and ends when the DATA polling (DQ7) is logical 1. DATA polling must be performed on addresses that fall within the sectors being erased. AS29F040 returns to read mode after sector erase unless DQ5 is set high by exceeding the time limit. Erase suspend allows interruption of sector erase operations to perform data reads from or writes to a sector not being erased. Erase suspend applies only during sector erase operations, including the timeout period. Writing an erase suspend command during sector erase time-out results in immediate termination of the time-out period and suspension of erase operation. AS29F040 ignores any commands during erase suspend other than read/reset, program, or erase resume commands. Writing the Erase Resume command continues erase operations. Addresses are DON'T CARE when writing Erase suspend or Erase resume commands. AS29F040 takes 0.2-15 s to suspend erase operations after receiving erase suspend command. To determine completion of erase suspend, check DQ6 after selecting an address of a sector not being erased. Check DQ2 in conjunction with DQ6 to determine if a sector is being erased. AS29F040 ignores redundant writes of erase suspend. While in erase-suspend mode AS29F040 allows reading data (erase-suspend-read mode) from or programming data (erase-suspend-program mode) to any sector not undergoing sector erase, treated as standard read or standard programming mode. AS29F040 defaults to erase-suspend-read mode while an erase operation has been suspended. Write the resume command 30h to continue operation of sector erase. AS29F040 ignores redundant writes of the resume command. AS29F040 permits multiple suspend/resume operations during sector erase. When attempting to write to a protected sector, DATA polling and Toggle Bit 1 (DQ6) are activated for about <1 s. When attempting to erase a protected sector, DATA polling and Toggle Bit 1 (DQ6) are activated for about <5 s. In both cases, the device returns to read mode without altering the specified sectors. )/$6+ Sector erase Erase suspend Sector protect 9 $//,$1&(#6(0,&21'8&725 ','#440533440$1#728233 0DUFK#5333 (R) $65<)373 6WDWXV#RSHUDWLRQV DATA polling (DQ7) Only active during automated on-chip algorithms or sector erase time outs. DQ7 reflects complement of data last written when read during the automated on-chip algorithm (0 during erase algorithm); reflects true data when read after completion of an automated on-chip algorithm (1 after completion of erase agorithm). )/$6+ )/$6+ )/$6+ )/$6+ )/$6+ )/$6+ )/$6+ )/$6+ Active during automated on-chip algorithms or sector time outs. DQ6 toggles when CE or OE toggles, or an Erase Resume command is invoked. When the automated on-chip algorithm is complete, DQ6 stops toggling and valid data can be read. DQ6 is valid after the rising edge of the fourth pulse of WE Toggle bit 1 (DQ6) during programming; after the rising edge of the sixth WE pulse during chip erase; after the last rising edge of the sector erase WE pulse for sector erase. For protected sectors, DQ6 toggles for <1 s during writes, and <5 s during erase (if all selected sectors are protected). Indicates unsuccessful completion of program/erase operation (DQ5 = 1). DATA polling remains active; CE powers the device down to 2 mA. If DQ5 = 1 during chip erase, all or some sectors are defective; during sector erase, the sector is defective (in this case, reset the device and execute a program or erase command sequence to continue working with functional sectors); during byte programming, that particular byte is defective. Attempting to program 0 to 1 will set DQ5 = 1. Checks whether sector erase timer window is open. If DQ3 = 1, erase is in progress; no commands will be accepted. If DQ3 = 0, the device will accept additional sector erase commands. Check DQ3 before and after each Sector Erase command to verify that the command was accepted. Exceeding time limit (DQ5) Sector erase timer (DQ3) During sector erase, DQ2 toggles with OE or CE only during an attempt to read a sector being erased. During chip erase, DQ2 toggles with OE or CE for all addresses. If DQ5 = 1, DQ2 toggles only at sector Toggle bit 2 (DQ2) addresses where failure occurred, and will not toggle at other sector addresses. Use DQ2 in conjunction with DQ6 to determine whether device is in auto erase or erase suspend mode. :ULWH#RSHUDWLRQ#VWDWXV Status Auto programming (byte) Program/erase in auto erase Read erasing sector In progress Erase suspend mode Read non-erasing sector Program in erase suspend DQ7 DQ7 0 1 Data DQ7 DQ7 0 DQ7 DQ6 Toggle Toggle No toggle Data Toggle Toggle Toggle Toggle DQ5 0 0 0 Data 0 1 1 1 DQ3 0 1 0 Data 0 0 1 0 DQ2 No toggle Toggle* Toggle Data Toggle* No toggle Toggle No toggle Auto programming (byte) Exceeded time limits Program/erase in auto erase Program in erase suspend * Toggles with Toggles with OE or CE only for erasing or erase suspended sector addresses. OE or CE only for erasing or erase suspended sector addresses. ','#440533440$1#728233 $//,$1&(#6(0,&21'8&725 : $65<)373 (R) $XWRPDWHG# RQ0FKLS# SURJUDPPLQJ# DOJRULWKP IRU#HDFK#E\WH Write program command sequence (see below) $XWRPDWHG#RQ0FKLS#HUDVH#DOJRULWKP Write erase command sequence (see below) )/$6+ DATA polling or toggle bit successfully completed DATA poll device-program Erase complete Programming completed Chip erase command sequence 5555h/AAh Sector erase command sequence 5555h/AAh Program command sequence 5555h/AAh 2AAAh/55h 2AAAh/55h 2AAAh/55h 5555h/80h 5555h/80h 5555h/A0h 5555h/AAh 5555h/AAh Program address/program data 2AAAh/55h 2AAAh/55h 5555h/10h Sector address/30h Sector address/30h Optional multiple sector erase commands* Sector address/30h * The system software should check the status of DQ3 prior to and following each subsequent sector erase command to ensure command completion. The device may not have accepted the command if DQ3 is high on second status check. ; $//,$1&(#6(0,&21'8&725 ','#440533440$1#728233 $65<)373 (R) '$7$#SROOLQJ#DOJRULWKP START 7RJJOH#ELW#DOJRULWKP START )/$6+ )/$6+ )/$6+ )/$6+ Read byte (DQ0-DQ7) Address = VA * Read byte (DQ0-DQ7) two times with OE toggling Address = don't care DQ7 = data? NO NO Is time elapsed = 1ms? NO YES DONE Does DQ6 toggle? NO DONE YES NO DQ5 = 1? DQ5 = 1? YES YES Read byte (DQ0-DQ7) Address = VA * YES Read byte (DQ0-DQ7) two times with OE toggling Address = don't care DQ7= data ? NO YES DONE Does DQ6 toggle*? NO DONE Issue Reset/read command Addr = X Data = F0h DONE YES * VA = Byte address for programming. VA = any of the sector addresses within the sector being erased during sector erase. VA = valid address equals any non-protected sector group address during chip erase. DQ7 rechecked even if DQ5 = 1 because DQ5 and DQ7 may not change simultaneously. Issue Reset/read command Addr = X Data = F0h * DONE DQ6 rechecked even if DQ5 = 1 because DQ6 may stop toggling when DQ5 changes to 1. ','#440533440$1#728233 $//,$1&(#6(0,&21'8&725 < $65<)373 (R) 3UHOLPLQDU\#LQIRUPDWLRQ 3URJUDPPLQJ#DOJRULWKP#IRU#FKLS Start VA* = 0000h Program byte with 00h ADDR =VA YES )/$6+ Is VA = VA_Start? Increment VA NO Increment VA Program byte with 00h ADDR = VA NO Is VA = 7FFFFh? YES Reset VA = 0000 Program byte with customer data ADDR =VA Verify data ADDR = VA NO Verify OK? NO Increment VA Is VA = VA_End**? YES YES NO Increment VA IncrementVA Is VA = VA_End? FAIL * VA = Current Address VA_Start = Starting Address ** VA_End YES PASS of Customer Code = Ending Address of Customer Code 43 $//,$1&(#6(0,&21'8&725 ','#440533440$1#728233 0DUFK#5333 (R) $65<)373 '&#HOHFWULFDO#FKDUDFWHULVWLFV Parameter Input load current A9 Input load current Output leakage current Output short circuit current * ** 9&&# #8133189 Symbol ILI ILIT ILO IOS ICC ICC2 ISB1 ISB2 VIL VIH VOL VOH1 VOH2 VLKO VID IOL = 12mA, VCC = VCC MIN IOH = -2.5 mA, V CC = VCC MIN IOH = -100 A, VCC = VCC MIN Test conditions VIN = VSS to VCC, VCC = VCC MAX VCC = VCC MAX, A9 = 12.5V VOUT = VSS to VCC, VCC = VCC MAX VOUT = 0.5V CE = VIL, OE = VIH CE = VIL, OE = VIH CE = OE = VIH, VCC = VCC MAX CE = VCC + 0.5V, OE = VIH, VCC = VCC MAX -0.5 2.0 2.4 VCC - 0.4 2.8 11.5 Min Max 1 90 1 200 30 60 1.0 400 0.8 VCC + 0.5 0.45 4.2 12.5 Unit A A A mA mA mA mA A V V V V V V V )/$6+ )/$6+ )/$6+ )/$6+ )/$6+ )/$6+ )/$6+ )/$6+ Active current, read @ 6MHz Standby current (TTL) Standby current (CMOS) Input low voltage Input high voltage Output low voltage Output high voltage Low VCC lock out voltage Input HV select voltage * Active current, program/erase Not more than one output tested simultaneously. Duration of the short circuit must not be >1 second. OUT = 0.5V was selected to avoid test problems caused by tester ground degradation. (This parameter is sampled and not 100% tested, but guaranteed by characterization.) The ICC current listed includes both the DC operating current and the frequency dependent component (@ 6 MHz). The frequency component typically is less than 2 mA/MHz with OE at VIH. ICC active while program or erase operations are in progress. ** 0D[LPXP#QHJDWLYH#RYHUVKRRW#ZDYHIRUP 20 ns +0.8V -0.5V -2.0V 20 ns 20 ns 0D[LPXP#SRVLWLYH#RYHUVKRRW#ZDYHIRUP VCC + 2.0V VCC + 0.5V + 2.0V 20 ns 20 ns 20 ns ','#440533440$1#728233 $//,$1&(#6(0,&21'8&725 44 $65<)373 (R) 3UHOLPLQDU\#LQIRUPDWLRQ $&#SDUDPHWHUV=#UHDG#F\FOH JEDEC Symbol Std Symbol tRC tACC tCE tOE tDF tDF tOH -55 Parameter Read cycle time Address to output delay Chip enable to output Output enable to output Chip enable to output High Z Output enable to output High Z Output hold time from addresses, CE or OE, whichever occurs first Min 55 0 Max 55 55 25 15 15 -70 Min 70 0 Max 70 70 30 20 20 -90 Min 90 0 Max 90 90 35 20 20 -120 Min 120 0 Max 120 120 50 30 30 -150 Min 150 0 Max 150 150 55 35 35 Unit ns ns ns ns ns ns ns )/$6+ tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tAXQX .H\#WR#VZLWFKLQJ#ZDYHIRUPV Rising input Falling input Undefined / don't care 5HDG#ZDYHIRUP tRC Addresses Addresses stable tACC CE tDF tOE OE WE tCE Outputs High Z tOH Output valid High Z 45 $//,$1&(#6(0,&21'8&725 ','#440533440$1#728233 0DUFK#5333 (R) $65<)373 $&#SDUDPHWHUV##ZULWH#F\FOH JEDEC Symbol tAVAV tAVWL tWLAX tDVWH tWHDX Std Symbol tWC tAS tAH tDS tDH tOES tOEH tGHWL tELWL tWHEH tWLWH tWHWL tWHWH1 tWHWH2 tGHWL tCS tCH tWP tWPH tWHWH1 tWHWH2 -55 Parameter Write cycle time Address setup time Address hold time Data setup time Data hold time Output enable setup time Output enable hold time: Toggle and DATA polling Read recover time before write CE setup time CE hold time Write pulse width Write pulse width high Programming pulse time Erase operation Min 55 0 40 25 0 0 10 0 0 0 35 20 15 0.3 Max -70 Min 70 0 45 30 0 0 10 0 0 0 35 20 15 0.3 Max -90 Min 90 0 45 45 0 0 10 0 0 0 45 20 15 0.3 Max -120 Min 120 0 50 50 0 0 10 0 0 0 50 20 15 0.3 Max Min 150 0 50 50 0 0 10 0 0 0 50 20 15 0.3 :(#FRQWUROOHG -150 Max Unit ns )/$6+ )/$6+ )/$6+ )/$6+ )/$6+ )/$6+ )/$6+ )/$6+ ns ns ns ns ns ns ns ns ns ns ns s sec :ULWH#ZDYHIRUP tWC Addresses 5555h tCH CE tGHWL;tOES OE tWP WE tCS A0h tDS tWPH tDH Program data :(#FRQWUROOHG 3rd bus cycle tAS Program address tAH DATA polling Program address tWHWH1 or 2 DATA VSS DQ7 DOUT ','#440533440$1#728233 $//,$1&(#6(0,&21'8&725 46 $65<)373 (R) 3UHOLPLQDU\#LQIRUPDWLRQ $&#SDUDPHWHUVZULWH#F\FOH#5 JEDEC Symbol Std Symbol tWC tAS tAH tDS tDH tOES tOEH tGHEL tWLEL tEHWH tELEH tEHEL tWHWH1 tWHWH2 tGHEL tWS tWH tCP tCPH tWHWH1 tWHWH2 -55 Parameter Write cycle time Address setup time Address hold time Data setup time Data hold time Output enable setup time Output enable hold time: Toggle and DATA polling Read recover time before write WE setup time WE hold time CE pulse width CE pulse width high Programming pulse time Erase operation Min 55 0 40 25 0 0 10 0 0 0 35 20 15 0.3 Max Min 70 0 45 30 0 0 10 0 0 0 35 20 15 0.3 -70 Max Min 90 0 45 45 0 0 10 0 0 0 45 20 15 0.3 -90 Max -120 Min 120 0 50 50 0 0 10 0 0 0 50 20 15 0.3 Max Min 150 0 50 50 0 0 10 0 0 0 50 20 15 0.3 &(#FRQWUROOHG -150 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns s sec )/$6+ tAVAV tAVEL tELAX tDVEH tEHDX :ULWH#ZDYHIRUP#5 DATA polling Addresses 5555h tWC WE tGHEL, tOES OE tCP CE tWS DATA A0h tDS tCPH tDH Program data DQ7 DOUT tWH tWHWH1 or 2 Program address tAS tAH Program address &(#FRQWUROOHG 47 $//,$1&(#6(0,&21'8&725 ','#440533440$1#728233 0DUFK#5333 (R) $65<)373 (UDVH#ZDYHIRUP tWC tAS 2AAAh 5555h tAH 5555h 2AAAh Sector address Addresses 5555h )/$6+ )/$6+ )/$6+ )/$6+ )/$6+ )/$6+ )/$6+ )/$6+ CE tGHWL OE tWP tWC tWPH tCS tDH 10h for Chip Erase 55h 80h AAh 55h 30h WE Data tDS AAh '$7$#SROOLQJ#ZDYHIRUP CE tCH tOE tDF OE tOEH WE tCE tOH DQ7 Input DQ7 tWHWH1 or 2 Output DQ7 Output High Z 7RJJOH#ELW#ZDYHIRUP CE tOEH WE OE DQ6 tDH tOE ','#440533440$1#728233 $//,$1&(#6(0,&21'8&725 48 $65<)373 (R) 3UHOLPLQDU\#LQIRUPDWLRQ (UDVH#DQG#SURJUDPPLQJ#SHUIRUPDQFH Limits Parameter Min - Typical 1.0 45 23 Max 10,000 Unit sec s sec cycles )/$6+ Sector erase and verify-1 time (excludes 00h programming prior to erase) Byte program time Chip programming time Erase/program cycles - - /DWFKXS#WROHUDQFH# Parameter Input voltage with respect to VSS on A9 and OE Input voltage with respect to VSS on all DQ, address and control pins Current Includes all pins except VCC. Test conditions: VCC = 5.0V, one pin at a time. Min -1.0 -1.0 -100 Max +13.0 VCC+1.0 +100 Unit V V mA $&#WHVW#FRQGLWLRQV Device under Test 100 pF* Test condition Output load VSS Unit 1 TTL gate 5 0.0-3.0 1.5 1.5 ns V V Input rise and fall times Input pulse levels Input timing measurement reference levels Output timing measurement reference levels *including scope and jig capacitance $EVROXWH#PD[LPXP#UDWLQJV Parameter Input voltage (Input or DQ pin) Input voltage (A9 pin, OE) Power supply voltage Operating temperature Storage temperature (plastic) Short circuit output current Symbol VIN VIN VCC TOPR TSTG IOUT Min -2.0 -2.0 -0.5 -55 -65 Max +7.0 +13.0 +5.5 +125 +125 200 Unit V V V C C mA NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Includes all pins except VCC. Test conditions: VCC = 5.0V, one pin at a time. 49 $//,$1&(#6(0,&21'8&725 ','#440533440$1#728233 0DUFK#5333 (R) $65<)373 5HFRPPHQGHG#RSHUDWLQJ#FRQGLWLRQV Parameter Supply voltage Input voltage Symbol VCC VSS VIH VIL Min +4.5 0 2.0 -0.5 Typ 5.0 0 Max +5.5 0 VCC + 0.5 0.8 Unit V V V V )/$6+ )/$6+ )/$6+ )/$6+ )/$6+ )/$6+ )/$6+ )/$6+ 7623#SLQ#FDSDFLWDQFH Symbol CIN COUT CIN2 Parameter Input capacitance Output capacitance Control pin capacitance Test setup VIN = 0 VOUT = 0 VIN = 0 Typ 6 8.5 7.5 Max 7.5 12 9 Unit pF pF pF 3/&&#SLQ#FDSDFLWDQFH Symbol CIN COUT CIN2 Parameter Input capacitance Output capacitance Control pin capacitance Test setup VIN = 0 VOUT = 0 VIN = 0 Typ 6 8.5 7.5 Max 7.5 12 9 Unit pF pF pF 'DWD#UHWHQWLRQ Parameter Minimum pattern data retention time Temp. (C) 150 125 Min 10 20 Unit years years ','#440533440$1#728233 $//,$1&(#6(0,&21'8&725 4: $65<)373 (R) 0DUFK#5333 3DFNDJH#GLPHQVLRQV h 1 2 3 4 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 5 6 7 8 9 10 11 12 13 14 15 16 j g 32-pin TSOP e f d c a b 4 5 6 7 8 9 10 11 12 3 2 1 32 31 30 29 28 27 26 i a 0-5 a b c d e f g h i j 32-pin TSOP min max (mm) (mm) 1.20 0.25 0.5 0.7 0.1 0.21 18.30 18.50 19.80 20.20 7.90 8.10 0.95 1.05 0.05 0.15 0.50 a b c d e f g h i j 32-pin PLCC typical (inch) 0.49 0.45 0.59 0.55 0.52 0.09 0.136 0.075 0.52 0.028 MS-016 AE 0.450 in. x 0.550 in. 0.110 in. 0.020 in. (min) 0.050 in. 0.004 in. (max) )/$6+ b JEDEC outline Body size Package thickness Board standoff Lead pitch Coplanarity 32-pin PLCC 25 24 23 22 21 d c e j 13 14 15 16 17 18 19 20 h f i g $65<)373#RUGHULQJ#FRGHVPackage \ Access time TSOP, 8x20 mm, 32-pin PLCC, 0.55x0.45", 32-pin 55ns 70 ns (commercial/industrial) (commercial/industrial) AS29F040-55TC AS29F040-55TI AS29F040-55LC AS29F040-55LI AS29F040-70TC AS29F040-70TI AS29F040-70LC AS29F040-70LI 90 ns (commercial/industrial) AS29F040-90TC AS29F040-90TI AS29F040-90LC AS29F040-90LI 120 ns (commercial/industrial) AS29F040-120TC AS29F040-120TI AS29F040-120LC AS29F040-120LI 150 ns (commercial/industrial) AS29F040-150TC AS29F040-150T AS29F040-150LC AS29F040-150LI $65<)373#SDUW#QXPEHULQJ#V\VWHP AS29F Flash EEPROM prefix 040 Device number -XXX Address access time X Package: L= PLCC T= TSOP X Temperature range: C = Commercial: 0C to 70C I = Industrial: -40C to 85C * Industrial and Commercial temperature range available 4; $//,$1&(#6(0,&21'8&725 ','#440533440$1#728233 DID 11-20011-A. Copyright (c)2000 Alliance Semiconductor Corporation (Alliance)'s three-point logo, our name, and IntelliwattTM are trademarks orregistered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this web site and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this web site. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or impliedwarranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, ex cept as expressly agreed to in Alliance's Terms and Conditions of Sale (available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights, mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use. |
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